SMVDU-TITAN-X
Silicon Core Boot Sequence Visualizer
Time:
0.0
ns
CHIP SILICON BOUNDARY (180nm CMOS)
AMBA AXI4 SYSTEM INTERCONNECT
HART 0-3
HART 4
Coherent L1 Cache
RoCC Neural Accelerator
RISC-V CPU Core Complex
State: Power-off
128KB eNVM
AES-256 Crypto
Secure Boot
Signature: Unchecked
L2 Bank 0
L2 Bank 1
L2 Directory Coherent Cache
Coherence: Idle
Gen2 x4 Controller
PIPE Serial Transceiver
PCIe High-Speed I/O
LTSSM: Power-off
MIPI CSI-2 Rx
HDMI TMDS Tx
Image Signal Processor (ISP)
Video Core Pipeline
Pipeline: Inactive
186 Source PLIC Matrix
CLINT Vector Block
Interrupt Hub
IRQ status: Idle
5x UART
2x SPI
2x I2C
2x CAN
Low-Speed
Idle
▶ Play
⏮ Event
Event ⏭
Speed:
1x
2x
5x
🔄 Reset