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Phase 4 — High-Speed Serial I/O Subsystems

Phase 4 expands the physical I/O boundary of the SMVDU-TITAN-X multicore processor SoC by integrating high-bandwidth serial communication interfaces.

1. High-Speed Interface Overview

  • Processor Cluster: Coherent Dual-Core RV64GC Rocket CPU cluster.
  • PCIe Gen2 x4 Controller:
    • Exposes high-speed differential TX and RX serial lanes.
    • Integrates a synthesizable Link Training and Status State Machine (LTSSM) supporting Gen2 (5 GT/s) clock speeds.
    • Mapped in the memory space at 0x5700_0000 with outbound memory-translation window at 0x6000_0000.
  • USB 2.0 OTG Controller:
    • Supports On-The-Go (OTG) host/device role negotiation.
    • Tristate buffers handle physical D+ (differential positive) and D- (differential negative) pad lines.
    • Mapped at 0x5600_0000.
  • HDMI 1.4 Transmitter:
    • Includes a dedicated DMA reader that sweeps the internal 16 MB frame buffer at 0x5800_0000.
    • Serializes active RGB frame data into three TMDS data channels and a clock channel.
    • Supports 640x480 resolution at 60Hz.

2. Chipyard Configuration Recipe

The dual-core, high-speed I/O SoC layout is defined inside the Chipyard package:

class TitanXPhase4Config extends Config(
  new freechips.rocketchip.subsystem.WithInclusiveCache ++                             // Coherent L2 Cache
  new chipyard.config.WithGPIO(address = 0x54010000, width = 32) ++                    // GPIO Controller
  new chipyard.config.WithSPIFlash(address = 0x10030000, fAddress = 0x20000000) ++     // SPI Flash Controller
  new freechips.rocketchip.rocket.WithNHugeCores(2) ++                                 // Dual-Core RISC-V Rocket Core
  new chipyard.config.AbstractConfig                                                   // baseline system
)

3. Verification Metrics

The SystemVerilog verification suite (tb_titan_x_phase4.sv) stimulates physical serial channels and verifies correct protocol handshakes in simulation:

================================================================
   SMVDU-TITAN-X PHASE 4 VERIFICATION RESULTS DASHBOARD        
================================================================
  Milestone 1: PCIe Gen2 x4 Link Training   |  [PASSED] (L0 Active)
  Milestone 2: USB 2.0 OTG Enumeration      |  [PASSED] (HS Mode)
  Milestone 3: HDMI 1.4 TMDS Clock Check    |  [PASSED] (P/N Clocks)
  Milestone 4: Diagnostic LED Mapping       |  [PASSED] (1111)
================================================================
  VERIFICATION METRICS: 100% SUCCESS
================================================================