Phase 1: Single-Core Bring-Up¶

Objective¶

Boot bare-metal firmware on a single Rocket RV64GC core, validate UART output, GPIO, and SPI, and establish a working Verilator simulation flow.

Success Criteria:
✅ Firmware boots and prints banner over UART
✅ LED heartbeat visible on FPGA
✅ Verilator simulation runs without RTL errors
✅ Phase 1 firmware builds cleanly with RISC-V GCC

Hardware Configuration¶

Memory Map (Phase 1)¶

Boot Sequence (Phase 1)¶

Power-On Reset
     │
     ▼
Boot ROM (0x0000_1000)
  └── Simple bootloader
     │
     ▼
SRAM Firmware (0x0800_0000)
  └── hello_uart/main.S
       ├── Initialize UART
       ├── Print boot banner
       └── LED heartbeat loop

Firmware¶

The Phase 1 firmware is in software/firmware/hello_uart/.

Build¶

# Install toolchain first
bash scripts/setup/setup_riscv_toolchain.sh
source ~/.bashrc

# Build
cd software/firmware/hello_uart
make

# Output files
build/hello_uart.elf   # ELF binary
build/hello_uart.hex   # Intel HEX (for simulation memory loading)
build/hello_uart.bin   # Raw binary (for FPGA BRAM)

Disassembly¶

make disasm
# View: build/hello_uart.dis

Simulation¶

Quick Simulation (RTL stub)¶

bash scripts/sim/run_verilator.sh

With Chipyard (Full)¶

conda activate chipyard
cd hardware/chipyard/sims/verilator
make CONFIG=smvdu.titan.x.TitanXSimConfig
./simulator-smvdu.titan.x.TitanXSimConfig \
    +max-cycles=10000000 \
    +loadmem=../../../../software/firmware/hello_uart/build/hello_uart.hex

Expected Output¶

  ╔═══════════════════════════════════════╗
  ║        SMVDU-TITAN-X  v0.1.0          ║
  ║   RISC-V RV64GC Open-Source SoC       ║
  ╚═══════════════════════════════════════╝

  [PHASE 1] Bare-Metal Bring-Up
  Core:  Rocket RV64GC (Single Core)
  Clock: 100 MHz
  UART0 initialized at 115200 baud
  LED heartbeat active

  SMVDU-TITAN-X ready!

Verification Checklist¶

• make in software/firmware/hello_uart/ succeeds
• make disasm produces correct RV64GC assembly
• Verilator lint passes on hardware/rtl/top/titan_x_top.v
• Verilator simulation runs with firmware HEX
• UART output matches expected boot banner
• GPIO LED heartbeat visible in simulation waveform

Tools Reference¶

References¶

• RISC-V Privileged ISA Spec v1.12
• Chipyard Documentation
• SiFive UART Spec
• Rocket Core